CPU in verilog

This is a project for the course Computer Architecture I took in 2023. I spent most of my time in July and August debugging the code and analyzing the waveforms on Vivado. I’ll primarily cover some parts of the pipelined CPU here.

Experiment setup

• Vivado

I had planned to use ModelSim but Vivado is just the right tool with abundant functionalities and clean interface. In the Vivado platform, circuit design code can be written using Verilog HDL and then synthesized, placed, and routed. It also provides a rich library of IP cores, accelerating the design and implementation process. Through Vivado’s simulation tools, designs can be verified and debugged to ensure functional and timing correctness. In this experiment, bitstreams were generated, and the pipelined CPU was also tested through simulation in Vivado before hardwired into the board.

• The Nexys A7 board

The Nexys A7 is a development board based on the Artix-7 FPGA, suitable for experiments in computer organization. It features a variety of peripheral interfaces, including buttons, switches, LEDs, seven-segment displays, and a VGA interface, making it convenient for connecting input/output devices. By using Verilog HDL and the Xilinx Vivado development suite, the designed circuit code can be loaded onto the Nexys A7 board for verification and debugging.

• The Venus platform

In this experiment, the Venus platform was used as the development and simulation environment for computer organization principles. Venus is an online experiment platform developed by UC Berkeley. It provides an interactive environment, so I could debug and assemble RISC-V assembly code.

Pipeline overall design

The schematic of the pipeline used in the experiment is shown in the figure.

• Some data paths in the single-cycle process are omitted in the diagram.
• The black arrows in the figure represent the direction of data transmission between modules.
• The circular modules represent components used to handle data hazards and control hazards, marked in blue.
• The diamond-shaped modules are used for updating the PC (Program Counter), marked in red.
• The cloud-shaped modules represent functionalities that are not implemented as separate Verilog files but are directly integrated within the CPU module.

The following section provides explanations for the key parts shown in the diagram.

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